1. Field of the Invention
The present invention relates generally to integrated circuit design and fabrication. More particularly, the invention relates to integrated circuit fabrication by specifying a high-level functional description of the circuit design.
2. State of the Art
Automated synthesis of a circuit layout design in response to user selected inputs is well known. Such automated synthesis typically requires the designer to prepare a textual description of the circuit layout using a hardware description language (HDL) wherein all functions needed to implement a desired data path in the circuit layout must be specified in detail. Further, the hardware description language must be used to specify all control functions needed by the data path to properly implement processing along the data path.
For example, a circuit layout may include a data path wherein specified bit locations of a first word are to be combined (e.g., added) with specified bit locations of a second word to produce an output. The designer may want to specify that the output should be rounded to the nearest integer value. Using a hardware description language, the designer must describe the Boolean functions (e.g., AND, OR, NOR functions) required to implement the addition of the first and second words. The designer must also describe the Boolean functions required to implement the rounding function. Further, Boolean control logic functions must be described to control the data path. For example, Boolean functions must be described for detecting the output of the adding operation so that this output is rounded up or rounded down (e.g., a fractional value of 0.7 would be rounded up while a fractional value of 0.3 would be rounded down).
In addition to describing the Boolean functions needed to implement the general data path functions and control logic functions, the designer must also examine the circuit in which the data path will be used to identify data path inputs. Where incompatibilities exist among the various inputs (e.g., different word lengths, different data formats and so forth), the designer must describe Boolean functions to correlate the inputs so that they can be properly combined. Similarly, the designer must specify Boolean functions to correlate the adding function output with an input to the rounding function, and to correlate the data path output with the circuit layout requirements.
Once the designer has described all behavioral aspects of the data path and attendant control logic, the description is input to a compiler which synthesizes a netlist of Boolean primitive gates (e.g., AND, OR, NOR gates). The netlist is produced by accessing a standard cell library of Boolean gates in the compiler's memory. The netlist is then translated into a transistor gate-level implementation for circuit layout fabrication.
The complex hardware description required for the relatively simple case of adding two words and rounding the resultant output requires tedious, time-consuming efforts by the designer. These efforts increase dramatically with an increase in data path complexity (and attendant increase in control logic complexity). The complexity of this conventional design and fabrication process makes adaptations of the data path to different circuit layouts difficult. The designer must re-describe the entire data path and control logic for each new implementation (e.g., changes in I/O characteristics and/or functional characteristics such as performance or operation). Further, the burden is on the designer to ensure that all behavioral aspects of the data path are accurately and fully described to ensure proper operation of the data path. Failure to describe all behavioral aspects of the data path and control logic can result in meaningless data path outputs. For example, a failure to describe the Boolean functions needed to render two inputs compatible, or the Boolean functions needed to account for adder overflow (i.e., where a maximum value of adder output is exceeded) can result in improper, meaningless data path outputs.